I attended the 51st Design Automation Conference (DAC) held at the Moscone Center in downtown San Francisco. DAC always has high quality technical presentations along with a very active and expansive exhibition hall.
One key point that was brought up in several talks was that with the complexity of SoC designs, verification needs to be addressed at the beginning stages, when decisions regarding architecture and high level system specifications are being made. There is design for test, but can there be “design for verification”? A very interesting “fractal” power management architecture was proposed, whose main aim was to be fully verifiable regardless of the number of nodes in the power management tree.
Security in general purpose processors (Intel and ARM secure computing architectures were outlined), and embedded systems (emphasis on automotive) was also a major focus throughout the conference!